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Full Job Description:-

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything and we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Business Area Description:-

Our Silicon Design & Verification businessis all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance-eliminating months off their project schedules.

We're looking for Physical Design Engineers in the role of Application Engineer.Does this sound like a good role for you

In this role you would be :

The primary focus of the Physical Design AE is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects. AE's are expected to possess Place & Route (physical) , Synthesis (logical and physical), STA experience and knowledge. PDAEs are expected to be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such asMacro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques. Additional knowledge of RTL Coding, Synthesis, Equivalency check, Constraints (timing & Power) is preferable.

Key Qualifications:

Passion for innovative solutions , exposure to cutting edge technology and positive approach to customer challenges

Design experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)

RTL to GDSII full flow experience or knowledge is preferable

Strong interest and understanding of Advanced Node & Design methodologies are required.

Deep Synopsys Back end tool (Logical and Physical Synthesis, Timing Closure techniques, Macro Placement, Routing at advanced Node , Static Timing Analysis, including noise analysis) experience and knowledge are required.

Excellent verbal and written presentation/communication skills are mandatory.

Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

BE/B.Tech/BS/MS/M.Tech or equivalent, required with 3+ years of experience/internship

Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2 OR Industry standard P&R tools) , Front end Synthesis and Formal Verification Tools

Tool knowledge (preferred) : front end Synthesis tools (Fusion Compiler, Design Compiler OR Industry standard synthesis tools),

Tool knowledge (preferred): STA (Primetime),

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.